The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 06, 1999
Filed:
May. 09, 1997
Patrice M Parris, Phoenix, AZ (US);
Yee-Chaung See, Phoenix, AZ (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A single level gate NVM device (10) includes p-channel and n-channel floating gate FETs (12, 14), an erasing capacitor (26), and a programming capacitor (28). The NVM device (10) is programmed by applying a programming voltage to the programming capacitor (28) and applying a ground voltage to the sources of the FETs (12, 14). The NVM device (10) is erased by applying an erasing voltage to the erasing capacitor (26) and applying ground voltage to the sources of the FETs (12, 14) and to the programming capacitor (28). Data is read from the NVM device (10) by sensing a voltage level at the drains of the FETs (12, 14) while applying a logic high voltage to the source of the p-channel FET (12), a logic low voltage to the source of the n-channel FET (14), and a reading voltage to the programming capacitor (28).