The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 06, 1999
Filed:
Jun. 17, 1996
Lloyd Hasley, Austin, TX (US);
Chris Hall, Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
Data processing system (800) and process (100) produce a hierarchical interconnection description of an integrated circuit design from a plurality of functional modules and a desired hierarchy. After an integrated circuit description is received (102), an interconnection structure is created (104) for each hierarchical level and functional module within the integrated circuit description. Based upon the desired hierarchy, a hierarchical tree is generated. Based upon the hierarchical tree, the interconnection structures are filled (106) with relevant interconnection and pin information to define interconnections among functional modules and hierarchical levels. After each interconnection structure is filled, a complete hierarchical interconnection description of the integrated circuit design has been completed. Finally, the hierarchical interconnection description is output (108). The present invention also includes generating a higher functional level description of an integrated circuit from a lower functional level description (300). Further included is a technique for generating integrated circuits based upon the present invention.