Multi-stage voltage-boosting circuit with boosted back-gate bias

Abstract

In a voltage-boosting circuit, field-effect transistors are coupled in series between an input terminal and an output terminal, and are coupled in parallel to respective capacitors which are driven by two complementary clock signals. The gate and drain of each field-effect transistor are interconnected. The field-effect transistors are disposed in at least two separate wells in a semiconductor substrate. Each well is coupled to one of the electrodes of one of the field-effect transistors in the well, providing an appropriate back-gate bias for the field-effect transistors in the well.