Apparatus and method for decoding instructions marked with breakpoint

Abstract

The invention specifies on-chip address matching hardware which is external to the processor core and prefetch queue of a microcontroller, and instruction decoding logic to mark and process breakpointed instructions. The address matching hardware includes a number of equality comparators which observe addresses on an intermodule bus of the microcontroller. This bus is not directly connected to the processor core and handles both instruction and data traffic. In one embodiment, four such matchers are provided. When an instruction address matches one of the breakpoints, a code indicating the breakpoint number is returned along with the instruction fetched. This breakpoint code is entered into the prefetch queue in the processor core, along with the instruction. When that instruction reaches the decode stage, the breakpoint information is decoded along with the instruction. The breakpoint actions associated with an instruction only occur when the instruction is about to be issued for execution. The decode logic of the processor core uses additional signals from the external matching hardware to determine if the breakpoint number associated with the current instruction is enabled to cause a breakpoint event. If the instruction is enabled to cause an event, the decode logic causes the event to happen. Regardless, the decode logic signals the external matching logic that a breakpointed instruction has been detected. When a breakpoint event is not enabled, the external matching logic can take other action such as updating a counter or starting execution monitoring activities.