Transparent data-triggered pipeline latch

Abstract

A system and method for transferring data between alternately evaluated first and second logic blocks of a dynamic logic pipeline. Associated with the system and method is a transparent data-triggered pipeline latch for controlling data flow between the first and second logic blocks. During an evaluation period accorded the first logic block, data existing at the logic block's data inputs is evaluated. Substantially simultaneously, the data-triggered latch is reset. As valid data is output from the first logic block, the latch is triggered. Immediately after the latch has been triggered, and before a clock-triggered evaluation period is accorded the second logic block, the data stored in the latch is output to the second logic block. Propagation of the early arriving data may be halted by ANDing the early arriving data signals with clocked signals which remain invalid. The invalid signals may comprise clock or data signals. Early arriving data is beneficial when supplied to static logic gates, or when transmitted through heavily loaded data lines which are associated with a propagation delay. A preferred embodiment of the latch comprises high and low level mousetrap data controls. Each control is coupled with a respective high or low level mousetrap data input, output, and storage node, and further comprises an input trigger, an input trigger disabler, a data storage device, a reset mechanism, and a reset disabler. The latch allows data to be driven out when valid, rather than in response to a clock edge.