Decoder circuit for a semiconductor memory device

Abstract

A semiconductor or memory device has a decoder circuit for decoding a plurality of external address signals. The external address signals include first and second external address signals. A first address buffer receives the first external address signals and outputs first internal address signals to first address lines. A second address buffer receives the second external address signals and outputs second internal address signals to second address lines. First predecoders have input terminals connected to the first address lines, and output first predecode signals to first predecode lines. Second predecoders have input terminals connected to the second address lines and output second predecode signals to second predecode lines. Main decoders have input terminals connected to the first predecode lines and the second predecode lines and output decode signals. The number of the first external address signals are greater than the number of the second external address signals. The second predecoders and the second predecode lines are provided at least in double in such a manner that inputs of the main decoders to be connected to each of the second predecode lines are equal in number to inputs of the main decoders to be connected to each of the first predecode lines. It is possible to shorten the transition time of predecode signals because of the same capacitive load of the predecoder circuit.