The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 30, 1999
Filed:
Aug. 20, 1997
Robert Meyer, Hamburg, DE;
Thomas Suwald, Hamburg, DE;
U.S. Philips Corporation, New York, NY (US);
Abstract
In a phase-locked loop comprising a phase detector (1), a loop filter (5) and a controlled oscillator (17) which are arranged on a common integrated circuit, interferences coupled into the substrate of the integrated circuit by other parts of the circuit are suppressed. In a first embodiment of the invention, this object is achieved in that the controlled oscillator (17) is preceded by a capacitive voltage divider (9) which comprises at least two capacitances (10, 12), the controlled oscillator (17) is controlled in dependence upon the output signal of the capacitive voltage divider (9), and the capacitive voltage divider (9), together with the phase detector (1), the loop filter (5) and the controlled oscillator (17) is arranged on an integrated circuit. In accordance with a second embodiment of the invention, the reduction of interference is achieved in that the controlled oscillator (17) has a differential structure and comprises at least two voltage-controlled current sources (18, 19) whose circuits are coupled to a power supply potential and to a substrate on which the integrated circuit is arranged, the controlled oscillator (17) has an output stage (20) which is arranged behind the voltage-controlled current sources (18, 19) and generates two differential digital signals in dependence upon the differential signals applied thereto, which differential digital signals are generated with a high edge steepness by means of switching between two potentials and are applied to amplifier stages (56, 57) which are arranged between power supply potential and reference potential and supply two differential output signals operating at reference potential.