The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 30, 1999
Filed:
Oct. 27, 1997
Simon J Lovett, Milpitas, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A NAND gate including a pull-down circuit coupled to a pull-up circuit. The NAND gate is configured to drive an output signal to a high logic state at a substantially uniform slew rate regardless of the number of input signals that are in a low logic state. The pull-up circuit may include a plurality of load circuits each coupled to a corresponding one of the plurality of input signals, and a plurality of transistor circuits each comprising a plurality of transistors coupled in parallel with each other and coupled to a corresponding one of the plurality of input signals or a complement of a corresponding one of the plurality of input signals. The plurality of load circuits and the plurality of transistors may each include a p-channel MOS (PMOS) transistor. The NAND gate may be incorporated into a decoder of a synchronous or asynchronous input path circuit to generally reduce the setup and hold time window of the input path circuit.