The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 1999

Filed:

Feb. 21, 1997
Applicant:
Inventors:

Robert M Lawson, Santa Clara, CA (US);

Jian Miremadi, Sunnyvale, CA (US);

Assignee:

Hewlett-Packard Company, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
257778 ; 257668 ; 257738 ; 257787 ;
Abstract

A chip-scale packaged integrated circuit and fabrication method are disclosed in which a semiconductor die and a rigid carrier of substantially identical geometric shape and size are aligned to form a packaged IC in which the die and carrier have a substantially 1:1 area ratio. A narrow gap between the die and carrier is bridged by the contact interconnections. An underfill material filling the gap and bonded to the die and carrier faces to relieve thermal expansion mismatch stresses. A fillet on one or more sides of the package is generally T-shaped in cross-section and nearly flat to the aligned side faces of the die and carrier. A fixture to facilitate fabrication of the package has a cavity with beveled sidewalls and seal which hold the die and carrier and form a narrow trough along the gap to receive and hold the underfill material adjacent the gap. The seal and cavity sidewalls have a surface to which the underfill material is nonadherent.


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