The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 1999
Filed:
Mar. 28, 1997
Ronald Gene Walther, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of isolating scan paths in an integrated circuit to reduce the RC delay associated with the scan paths and reduce power consumption, and to further enhance the capacitive decoupling of the power supply to reduce noise. The scan path can be connected to a data-storage element (latch or flip-flop) by a CMOS transmission gate, a single PMOS or NMOS transistor, or a logic gate (such as a NAND gate). The data-storage element is tested using either a scan-enable line, or the scan clock which is also connected to the data-storage element as an input. When the scan-enable line (or scan clock) is turned on, the scan path is connected to the output of the data-storage element.