The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 1999
Filed:
Jul. 15, 1997
Satoshi Sugawa, Tokyo, JP;
Shiro Hosotani, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
An output from an adder 10.sub.1, i.e., an output of a first bit plane is inputted to an adder 10.sub.6 through delay elements 2.sub.2 and 3.sub.0 and a multiplier 100.sub.0. On the other hand, input data X are inputted to multipliers C.sub.2.sup.1 to C.sub.0.sup.1 through a delay element 1.sub.0 and multiplied by the respective multipliers to obtain partial products. An adder 10.sub.2 receives a partial product by the multiplier C.sub.2.sup.1 through a delay element 2.sub.3 and a partial product by the multiplier C.sub.1.sup.1. An adder 10.sub.3 receives an output from the adder 10.sub.2 through the delay element 2.sub.3 and on the other hand a partial product by the multiplier C.sub.0.sup.1. An output from the adder 10.sub.3, i.e., an output of a second bit plane is inputted to the adder 10.sub.6 through a delay element 2.sub.5. The adder 10.sub.6 performs addition of the output from the adder 10.sub.3, i.e., the output of the second bit plane and the output from the adder 10.sub.1, i.e., the output of the first bit plane, to output the addition result. This structure allows reduction in the number of delay elements and adders, to achieve a filter circuit downsized in circuit scale.