The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 1999
Filed:
Aug. 05, 1996
Creigton Asato, San Jose, CA (US);
Fujitsu Limited, Kanagawa, JP;
Abstract
A circuit combines the functions of a logic gate and a latch to lower steady state power dissipation during gate operation. The circuit operates in two modes: a flow-through mode and a latched mode. In the flow-through mode, a gate portion which receives one or more digital input signals implements the complement of a desired Boolean logic function on the input signals and provides an internal signal. The gate portion may have a steady-state power dissipation while providing the internal signal. An inverter in a latch portion of the circuit inverts the internal signal to generate an output signal which represents the desired logical combination of the input signals. The inverter provides the output signal with a full-range CMOS voltage. In latched mode, the gate portion is disabled to stop the steady-state power dissipation while the latch portion of the circuit preserves the desired output signal.