The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 1999

Filed:

May. 31, 1996
Applicant:
Inventor:

Paul L Perez, Fort Collins, CO (US);

Assignee:

Hewlett-Packard Company, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
326 93 ; 326 97 ;
Abstract

An evaluation phase expansion system for increasing the operating frequency of a dynamic logic circuit which includes a plurality of logic stages. The plurality of logic stages are partitioned into a first set of logic stages which are responsive to an early clock signal and which evaluate in an early evaluate phase and a second set of logic stages which are responsive to a late clock signal and which evaluate in a late evaluate phase. The late evaluate phase of the late clock signal commences during the early evaluate phase of the early clock signal and terminates during an early pre-charge phase of the early clock signal in order to artificially induce clock asymmetry to compensate for logic asymmetry in alternating pipeline phases of the dynamic logic circuit.


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