The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 1999

Filed:

Jul. 28, 1997
Applicant:
Inventors:

Janet Kirkland, Fremont, CA (US);

Mark R Schneider, San Jose, CA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
438106 ; 438106 ; 438118 ; 438126 ;
Abstract

An integrated circuit package having a die supported on a ball grid array substrate and wire bonds electrically connecting the die to the substrate. Supported on the substrate is a lock ring having a threaded opening encircling the die. Encapsulant covers the die and the wire bonds and adheres the lock ring to the substrate. A heat sink having a threaded portion can be threaded into the lock ring into an operative cooling position relative to the die and subsequently to an unthreaded removed position. When in the latter position, a repair station can be positioned over the package and the solder balls are accessible for hot gas melting thereof for removal (or replacement) of the package from the underlying motherboard.


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