The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 1999
Filed:
Mar. 18, 1997
Anantakotiraju Vegesna, Austin, TX (US);
Jayachandra B Avula, Austin, TX (US);
Peter H Jewett, Austin, TX (US);
Yatin G Mundkur, Austin, TX (US);
Vinay J Naik, Austin, TX (US);
James E Monaco, Austin, TX (US);
Ross Technology, Inc., Austin, TX (US);
Abstract
An apparatus and method for scheduling the execution of one or more of a sequence of instructions for superscalar execution by a central processing unit during a single clock cycle of the processor clock is disclosed wherein the scheduling process is performed in a manner which does not dictate the duration of the processor clock period. During the decode stage of the processor pipeline, the instructions are classified, decoded, and data and resource dependencies are detected and resolved for operand access, with these processes being performed virtually in parallel so that the instructions can be appropriately scheduled for execution at the beginning of the next processor clock cycle. Because of the parallel nature of the scheduling process, scheduling can be performed and completed fast enough that processes other than instruction scheduling will dictate the minimum processor clock period.