The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 16, 1999

Filed:

May. 01, 1997
Applicant:
Inventor:

Mikio Fukushi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03D / ;
U.S. Cl.
CPC ...
375376 ; 327156 ;
Abstract

In a DPLL circuit used in a receiver for radio data communication employing the GMSK modulation system, a data latch circuit 23 and subtractor 24 find the phase information difference for each symbol from the incoming phase data. A modulation component removal circuit 25 removes the modulation component from the phase information difference. A frequency error calculating circuit 26 integrates the phase information difference over an interval of n symbols, multiplies this integrated value by 1/n, and takes the result as the mean frequency error value for the interval of n symbols, and then outputs this to loop filter 32. A phase error calculating circuit 27 further integrates over an interval of n symbols the integrated value from the frequency error calculating circuit, and multiplies the result by 2/n. Adder 28 adds an initial phase latched by a data latch circuit 22 to the output of the phase error calculating circuit, and outputs the result to NCO 33 as the phase error value. Operation of loop unit 36 is commenced with a timing that is preset by the mean frequency error value and phase error value.


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