High speed semiconductor memory with burst mode

Abstract

A semiconductor memory device has an input circuit for inputting reference clocks, an input buffer circuit for latching external input signals in synchronization with the reference clocks, and an output buffer circuit for outputting a stored data to an outside in synchronization with the reference clocks. The input buffer circuit and the output buffer circuit are caused to operate at respectively different edges of the reference clocks for processing one and the same stored data. The device may include an internal read-out circuit system which reads-out the stored data in accordance with the external input signal and which is caused to operate solely based on an edge at which the input buffer circuit operates. Between the internal read-out system and the output buffer circuit, there is provided a buffer circuit which temporarily stores the stored data read-out by the internal read-out circuit system until the stored data is outputted by the output buffer. The arrangement enables the provision of a high burst mode memory device in which almost no additional gate delay and no increase in its area.