Semiconductor device having multiple sized memory arrays

Abstract

A semiconductor memory device is provided that enhances data output speed. The semiconductor uses dual memory arrays with differing activation voltage levels. The semiconductor memory includes a first memory cell array having multiple memory cells and a second memory cell array having more memory cells than the first memory cell array. First and second row decoders respectively receive first and second row addresses to respectively generate an activation signal for a word line in the first memory cell array and subsequent word lines in the second memory cell array. A column decoder receives and decodes a column address to generate a bit line selection signal for the first and second memory cell arrays. The semiconductor device further includes a sense amplifier, which is coupled to bit lines selected based on the bit line selection signals, that detects a potential difference between the bit lines caused by data and amplifies the potential difference. The sense amplifier also refreshes the data on the memory cell from which the data was read.