The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 1999
Filed:
Apr. 14, 1997
Ichiro Kumata, Kanagawa, JP;
Masatoshi Aikawa, Kanagawa, JP;
Sony Corporation, , JP;
Abstract
It is to realize a function clock generation circuit with which a wiring area and cell area, and further a power consumption can be reduced, and a timing design is easy. An input terminal D of a through latch circuit LTC11 is connected to an input line of an enable signal EN, an inversion clock input terminal G is connected to the input line of the clock signal, one input terminal of a NAND gate NAND11 is connected to an output terminal Q of a through latch circuit LTC11, the other input terminal is connected to the input terminal of the clock signal CK, and the output terminal is connected to the input terminal of an inverter INV11. Then, in the through latch circuit LTC11, the enable signal EN is sampled at the rising edge of the clock signal CK, and according to the value, the clock pulse immediately after the sampling is passed or blocked by the logical gate LGT comprising a NAND gate NAND11 and an inverter INV11.