Method of fabricating a self-aligned double polysilicon npn transistor

Abstract

A method of forming a double polysilicon NPN transistor using a self-aligned process flow. The method includes use of a sacrificial oxide layer deposited over an epitaxial silicon layer prior to deposition and doping of the polysilicon layer from which the base electrode is formed. The sacrificial oxide layer acts as an etch stop for the plasma etch used to pattern the polysilicon layer. After patterning of the doped polysilicon layer, the sacrificial layer is removed using a wet etch. Etching of the oxide layer is performed in a manner which undercuts the doped polysilicon layer. Polysilicon is then deposited by a CVD process in the undercut region from which the initial polysilicon layer has been removed. The CVD deposited polysilicon fills in the gap between the doped polysilicon layer and the underlying epitaxial silicon layer caused by the oxide etch. The CVD deposited polysilicon is then oxidized. The portion of the CVD deposited polysilicon between the doped polysilicon layer and the single crystal silicon remains unoxidized. The oxidized CVD deposited polysilicon is then etched to form sidewall spacers. A second polysilicon layer is then deposited over the substrate and then implanted with an appropriate N+ type dopant. The transistor structure is then annealed to form junctions for the device.