Bus interface unit capable of simultaneously proceeding with two bus

Abstract

A bus interface unit of a microprocessor which can simultaneously process bus cycle's requests coming from various pipelines during for one cycle in the pipelined high-performance microprocessor of a superscalar type. The bus interface unit includes a bus cycle arbiter for arbitrating a plurality of cycle requests inputted from a plurality of units, a cycle multiplexer for selecting cycle information inputted from the units in response to an arbitration determination of the bus cycle arbiter, a cycle queue for storing selected information, a cycle generator for generating a bus cycle in response to the information stored in the cycle queue, a bus controller for controlling the bus interface unit as a whole, and a write buffer for enabling a next operation without waiting for the core unit to complete its write operation to improve a performance of a memory write cycle. According to the bus interface unit, the bus cycle requests from respective pipelines of the microprocessor are simultaneously processed during one cycle.