Decode register with scan functionality

Abstract

A decode register which receives a first plurality of input lines. If the decode register is not in a scan mode during a given clock cycle, the decode register is configured to convey a decoded output value in response to an input value conveyed on the first plurality of input lines. The decode register also includes a scan decode unit, which receives a second plurality of input lines. When operating in scan mode during a given clock cycle, the decode register is configured to convey a second decoded output value in response to a second input value conveyed on the second plurality of input lines. The second plurality of input lines comprise a scan input line and one or more feedback lines which each correspond to a value on the scan input line during a previous clock cycle. The decode register also includes an encoder which is configured to receive a value indicative of the second decoded output value. In response to receiving the decoded input value, the encoder is configured to convey a corresponding encoded output value on a scan output line and the one or more feedback lines. The encoder implements a serial shift function for the scan input of the decode register. In this manner, a single scan input bit may be used to test each of a plurality of output lines while ensuring only one output line is active at a time. Additionally, with only a single logic stage, the decode register exhibits reduced propagation delay.