The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 09, 1999
Filed:
May. 02, 1997
Gi-won Cha, Suwon, KR;
Samsung Electronics, Co., Ltd., Suwon, KR;
Abstract
A burn-in stress control circuit for an integrated memory device, such as DRAM, includes a first logic gate for receiving a burn-in enable signal and outputting an inverted burn-in enable signal, a resistor having a first terminal connected to the input terminal of the first logic gate, a first capacitor connected between the second terminal of the resistor and ground. A first transistor having a control terminal connected to the second terminal of the resistor and a first main terminal connected to a source voltage, is activated only when the burn-in enable signal is a high logic signal, thereby outputting the source voltage to a second main terminal of the first transistor. A second transistor having a control terminal connected to an output terminal of the first logic gate, a first main terminal connected to ground and a second main terminal connected to the second main terminal of the first transistor, is activated only when the burn-in enable signal is a low logic signal. Thus, peak current applied to a memory cell array, and noise can be reduced.