The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 09, 1999
Filed:
Jun. 27, 1997
George M Ansel, Starkville, MS (US);
Jeffery S Hunt, Ackerman, MS (US);
Satish Saripella, Starkville, MS (US);
Sudhaker Reddy Anumula, Starkville, MS (US);
Ajay Srikrishna, Sunnyvale, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A memory device includes a random access memory (RAM) cell accessible through a RAM wordline and coupled between first and second bitlines; a read only memory (ROM) cell accessible through a ROM wordline and having an output coupled to the first bitline and an input configured to receive a first voltage signal; and a reference voltage generator having a first input coupled to the first bitline, a second input configured to receive the first voltage signal, and an output coupled to the second bitline. The memory device may further include a bitline load having an output coupled to the first bitline. A virtual ground driver configured to produce the first voltage signal may be coupled to the input of the read only memory cell. Further, column select pass gates configured to be under the control of a logic signal and having a first input coupled to the first bitline, a second input coupled to the second bitline, a first output and a second output may be provided. A sense amplifier having a first input coupled to the first output of the column select pass gates and a second input coupled to the second output of the column select pass gates may be included in the memory device. The memory device may be read by modulating a first voltage input to the sense amplifier using a second voltage input to the sense amplifier.