Flexible circuitry and method for detecting signal patterns on a bus

Abstract

Circuitry for detecting signal patterns on a multi-bit bus. First comparison circuitry monitors a first portion of the bus comparing it with a first expected signal pattern, generating a first comparison output. Second comparison circuitry monitors a second portion of the bus comparing it with a second expected signal pattern, generating a second comparison output. Both comparison outputs are applied to an AND gate and a first OR gate. One data input of a multiplexer is coupled to the output of the first OR gate. Another data input is coupled to the output of the AND gate. Another data input is coupled to the first comparison output, and another data input is coupled to the second comparison output. One input of a second OR gate may be coupled to the multiplexer output, and another input coupled to a disable indicator, allowing the multiplexer output to be overridden. The first and second comparison outputs may be generated by bit-wise comparing first and second portions of the bus with first and second expected signal patterns. The logical AND of the respective comparison results may be treated as the first and second comparison outputs, or they may be treated as first and second intermediate bits. These first and second intermediate bits may be ORed with first and second mask bits, and the results may be treated as the first and second comparison outputs. The outputs of the two OR operations may also be EXCLUSIVE ORed with first and second negate bits, respectively.