Input and output buffer circuit

Abstract

An input and output buffer circuit which is contained in a first circuit operated on a first power source of a first voltage level Vcc1 and is permitted to connect to a second circuit operated on a second power source of a second voltage level Vcc2 higher than the first voltage level Vcc1 including: a driver PMOS transistor with a CMOS gate; a PAD terminal serving as an input and output terminal; and means for controlling the potential of the N well of the driver PMOS transistor in such a manner that when the potential at the PAD terminal is less than Vcc1-Vth, wherein Vth is a threshold voltage of a MOS transistor contained between the driver PMOS transistor and the PAD terminal, the potential of the N well is set at the first voltage level Vcc1; when the potential at the PAD terminal is more than Vcc1+Vth, the potential of the N well is equated with the potential at the PAD terminal; and when the input and output buffer circuit is in the output mode the potential of the N well is switched to the first voltage level Vcc1, whereby the noise resistance and the latch-up resistance of the input and output buffer circuit are improved while preventing a path current flowing through the driver PMOS transistor.