The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 1999

Filed:

Jun. 06, 1997
Applicant:
Inventors:

Naoyuki Urasaki, Shimodate, JP;

Kouichi Tsuyama, Shimodate, JP;

Kazuhito Kobayashi, Yuki, JP;

Norio Okano, Tsukuba, JP;

Hiroshi Shimizu, Shimodate, JP;

Nobuyuki Ogawa, Tsukuba, JP;

Akishi Nakaso, Oyama, JP;

Toyoki Ito, Shimodate, JP;

Daisuke Fujimoto, Shimodate, JP;

Kazuhisa Otsuka, Shimodate, JP;

Shigeharu Arike, Tochigi-ken, JP;

Yoshiyuki Tsuru, Shimodate, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B44C / ;
U.S. Cl.
CPC ...
216 18 ; 216 20 ; 216 34 ; 216 65 ;
Abstract

A multilayer printed circuit board small in interlayer thickness, capable of fine wiring, minimized in IVH and BVH diameters, high in strength and also excellent in wire bonding workability can be produced by a process comprising the steps of coating a thermosetting resin varnish compounded with electrically insulating whiskers on a roughened side of a copper foil, semi-curing the resin by heating to form a thermosetting resin layer, integrally laminating it on an interlayer board in which plated through-holes and conductor circudits have been formed, and roughening the cured thermosetting resin layer on the via hole wall surfaces with a roughening agent.


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