The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 1999

Filed:

Jul. 30, 1996
Applicant:
Inventors:

Kazuya Yamamoto, Tokyo, JP;

Kosei Maemura, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B / ; H04L / ; H03G / ;
U.S. Cl.
CPC ...
455 83 ; 455 78 ; 455 79 ; 455 80 ; 455 81 ; 455269 ; 455281 ; 330277 ; 330130 ; 333 18 ; 333 171 ; 333 81 ;
Abstract

An integrated circuit includes a single pole double throw switch including a transmitting and receiving port, a transmitting port, and a receiving port. A transmission switch is coupled between the transmitting port and the transmitting and receiving port. A reception switch is coupled between the receiving port and the transmitting and receiving port. The reception switch includes a field effect transistor having a gate, a drain and a source. A voltage generating circuit receives first and second power supply voltages. The first power supply voltage is greater than the second power supply voltage. The voltage generating circuit generates a third voltage lower than the second power supply voltage and applies the third voltage to the gate of the field effect transistor of the reception switch during transmission. As a result, the magnitude of the voltage difference between the gate and the source or the gate and the drain of the second field effect transistor is greater than the magnitude of the difference between the first and second power supply voltages. Accordingly, because of the increased electrical separation between the terminals of the field effect transistor, leakage current flowing to the receiving port during transmission is reduced.


Find Patent Forward Citations

Yamamoto, Kazuya. (1999). Integrated circuit (U.S. Patent No. 5878331). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5878331

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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