The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 1999

Filed:

Jan. 10, 1997
Applicant:
Inventors:

Lars Wolfgang Liebmann, Poughquag, NY (US);

Robert T Sayah, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364488 ;
Abstract

A method is provided that automatically generates compensated semiconductor devices based on existing VLSI CAD database circuit designs. The preferred method forms a plurality of edge projection shapes which are intersected with active area shapes to form gate edge shapes. The gate edge shapes and residual of the edge shapes are the sorted according to their relative position. These shapes are then selectively biased according to their relative position, and then are used to compensate the existing gate conductor shapes. Thus, this method provides a way to generate gate structures with compensated gate lengths for n-channel and p-channel devices based on existing gate, diffusion and implant designs. This system has the advantage of generating designs with detailed attention to the placement and minimization of jogs that negatively impact the lithography performance.


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