The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 1999

Filed:

Oct. 18, 1996
Applicant:
Inventors:

Ho D Truong, San Jose, CA (US);

Edward H Yu, Newark, CA (US);

Kathy Ying Chen, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
327 99 ; 327298 ; 327407 ;
Abstract

An apparatus for multiplexing a pair of test clock signals and a pair of system clock signals onto a pair of output clock signals includes a first means for coupling a first test clock signal to a first output clock signal when a test mode control signal is active, for driving the first output clock signal to an inactive clock signal level when the test mode control signal transitions to an inactive state, and for coupling a first system clock signal to the first output clock signal beginning with a first full clock pulse of the first system clock signal which occurs after the test mode control signal transitions to the inactive state. The apparatus further includes a second means for coupling a second test clock signal to a second output clock when the test mode control signal is active, for driving the second output clock to the inactive clock signal level when the test mode control signal transitions to the inactive state, and for coupling a second system clock signal to the second output clock beginning with a first full clock pulse of the second system clock signal which occurs after the first full clock pulse of the first system clock signal. When exiting the test mode the apparatus ensures that both first and second output clock signals are brought (or held) to an inactive clock signal level, and that system operation begins with the first system clock signal.


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