The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 1999

Filed:

Feb. 18, 1997
Applicant:
Inventor:

Tapio Kuiri, Oulu, FI;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02J / ;
U.S. Cl.
CPC ...
307 38 ; 307 29 ; 326 63 ; 326102 ; 327434 ; 320125 ; 455343 ; 455572 ;
Abstract

A wireless communicator, such as a cellular telephone or personal communicator, includes a power source (e.g., two series connected batteries) providing output voltages VSS, VDD, and V1, where V1=(VDD-VSS)/2. The power source is coupled to a first load for powering the first load with VSS and VDD. The wireless communicator further includes a power source switching unit having first inputs coupled to VSS, VDD and V1, a second input coupled to a MODE signal, and outputs coupled to a second load. The power source switching unit is responsive to a first state of the MODE signal for powering the second load with VSS and V1, and is responsive to a second state of the MODE signal for powering the second load with V1 and VDD. By periodically toggling the MODE signal, such as at a frame rate of the wireless communicator, the power drawn from each battery by the second load is equalized, while providing the second load with a desired lower operating voltage. Also shown is interface circuitry for level shifting signals output from the first load to the second load, and signals output from the second load to the first load. The interface circuitry is also responsive to the state of the MODE signal for accommodating the changes in levels of the second load input/output signals between VSS-V1, and V1-VDD.


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