The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 02, 1999
Filed:
Mar. 26, 1997
Jack L Jewell, Boulder, CO (US);
Picolight Incoporated, Boulder, CO (US);
Abstract
An improved semiconductor device is provided. The semiconductor device comprises a first layer on a restricted growth surface having a first central region with a transverse dimension D and having a first average lattice constant L.sub.1 within the first central region; a first, last and at least one intermediate transition layers, the transition layers forming a transition region, the transition region disposed above the first layer, the transition region having a vertical thickness T, and where at least one of the intermediate transition layers has average lattice constants between L.sub.1 and a second average lattice constant L.sub.c where the first transition layer has a lattice constant closer to the L.sub.1 than L.sub.c and the last transition layer has a lattice constant closer to the L.sub.c than L.sub.1 ; and a second layer disposed on the transition region, the second layer having a second average lattice constant L.sub.2, the second layer having a second central region having the average lattice constant L.sub.c and an average lattice constant L.sub.3 outside of the second central region, and where L.sub.c does not equal L.sub.3 ; wherein: the transition region has an average fractional change in lattice constant characterized by .kappa. where .kappa.=(D/T) {(L.sub.c -L.sub.1)/L.sub.1 }, where .vertline..kappa..vertline.<18 and wherein a lattice mismatch .vertline.L.sub.c -L.sub.1 .vertline./L.sub.1 .gtoreq.0.0014. Additionally, various preferred semiconductor substrates, transition regions and active regions are discussed.
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