Register selection system and method

Abstract

A register selection system increases a speed for selection of memory registers when selection is based upon a constant K defined by a sum of two numbers. The register selection system includes a specialized predecoder interconnected with a specialized decode array. The predecoder has first and second address inputs. The predecoder is configured to process first and second address values each of width n on the first and second address inputs respectively in order to produce first, second, third, and fourth predecoded values of width n on respective predecoder outputs. The first, second, third, and fourth predecoded values have respective widths of n+1, n, n, n-1. The decode array, which is connected to the predecoder outputs, is configured to receive the predecoded values. The decode array has 2.sup.n+1 register select outputs corresponding respectively with registers. The decode array is configured to assert one of the register select outputs, while deasserting a remainder of the register select outputs, based upon the predecoded values. As a result, a determination is made as to when the two numbers equal the constant K without performing a summing operation and a carry propagation associated with the summing operation. Moreover, a selection of the one register is accomplished based upon the determination.