The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 1999
Filed:
Mar. 25, 1997
Dhimant Patel, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method of modeling a pullup device and a pulldown device with delay back annotation in accordance with the VITAL application specific integrated circuit modeling specification. The modeling method comprises the steps of modeling an entity and creating an identity primitive procedure which delays an input signal by a value specified in a timing generic and also preserves the signal shape. The procedure is then used to perform state pre-mapping of the incoming signal to preserve the identity of selected states (including all states). The delayed and pre-mapped signal forms the input to a VITAL state table to model the behavior of the device. The identity primitive procedure is then used to post-map the resulting signal in order to recover the selected states of the input signal. By altering the state pre- and post-mapping tables, either pullup or pulldown, both with delay back annotation may be modeled using the functions and procedures of the VITAL specification.