The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 1999
Filed:
Jun. 13, 1996
David B Rees, Hants, GB;
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
An improved I/O cell is disclosed which includes a combined p-channel and n-channel transistor pullup configuration. In particular, such combination is connected in series between the chip operating voltage V.sub.cc, and the I/O cell output pad. The n-channel transistor is biased substantially continuously on its gate terminal with a pumped voltage from a charge pump, which permits it to pass voltages up to and including V.sub.cc. The p-channel transistor operates in its normal fashion, controllable via a pullup select signal applied to its gate terminal to pull the pad high. During normal operation, the n-channel transistor is always ON, thus reducing the substantial dynamic current drawn from the charge pump. The voltage appearing on the pad is fed back to a second n-channel transistor. When the voltage on the pad exceeds V.sub.cc for example, a 5 volt signal when V.sub.cc is 3.3 volts), the second n-channel transistor switches the gate of the first n-channel transistor to a reference signal, which is a diode drop below V.sub.cc. The first n-channel transistor, in response thereto, shuts-off, thus protecting the p-channel pullup transistor from the excessive voltages appearing on the pad.