The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 1999
Filed:
Jun. 12, 1996
Andre Stolmeijer, Santa Clara, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method of fabricating an integrated circuit with trenches, without parasitic edge transistors, for isolating FET transistors from each other without degrading the FETs operating characteristics by junction leakage, breakdown or shorting, when a metal silicide is used in the source/drain regions. A silicon wafer is formed with sidewalls on the sides of each area in which a groove is to be etched. In etching the silicon, the sidewalls define the lateral dimension of the trenches. After the trenches are etched, the sidewalls are removed and the trenched are filled with an insulating material using a high density plasma reactor, such as an electron cyclotron resonance (ECR) plasma reactor. This type of reactor simultaneously deposits and sputter etches so that silicon edges at the base of the now removed sidewalls become tapered at an angle of about 45.degree. during deposition. Thus, the profiles of the filled trenches all have tapered tops which reduces the possibility of parasitic edge transistors and any leakage or shorting.