The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 1999
Filed:
May. 03, 1996
Applicant:
Inventors:
Roland T Knaack, Starkville, MS (US);
Brian P Evans, Starkville, MS (US);
Assignee:
Cypress Semiconductor Corp., San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371 491 ; 371 211 ; 365201 ; 39518505 ;
Abstract
The present invention provides a circuit and method for generating a parity bit and checking the parity of data words positioned in the read data path of a memory device or buffer. The parity check mode can detect errors. The parity generation mode generates EVEN or ODD parity as an additional bit. Other devices in the system may generally be configured to accept either EVEN or ODD parity. The parity generation and checking circuit can detect errors in both the data input to the buffer as well as errors created in the storage of the data by the buffer.