Distributed switch buffer utilizing cascaded modular switch chips

Abstract

A distributed switch buffer and method for switch buffer enlargement use standard switch chips as modules that are cascaded in multiples to provide arbitrarily large switch buffers for any number of inputs and outputs. Any type of packet switch chip may be used in any combination. A packet that enters the first switch chip in the cascade automatically gets transferred to other switch chips as part of an integrated buffering scheme. Every input of the switch is connected to all of the switch chips in the first stage of the distributed buffer. The queue of each output of the switch is then expanded by adding more stages of switch chips. All outputs of each switch chip go to the inputs of the same switch chip in the next stage of the distributed buffer so that all of the buffer space of all the cascaded switch chips is available to each input port. The queue may be expanded indefinitely by cascading more chips. In one embodiment, inputs are connected to all the cascaded switch chips for each output port so that each chip only needs to have one output. The number of inputs for each switch chip in the intermediate stages need not equal the number of outputs from that stage, and it is possible to use a different number of cascade stages for each switch output port.