Apparatus and method for verifying the timing performance of critical

Abstract

A method of improving the timing performance of a circuit includes the step of producing a first set of timing results from a static timing analyzer operating on a netlist that characterizes a circuit. A critical timing path within the circuit is then identified from the first set of timing results. The critical timing path is then converted into an equivalent schematic circuit representation. A simulation of the equivalent schematic circuit representation on a circuit simulator produces a second set of timing results. Timing discrepancies are then located between the first set of timing results and the second set of timing results. Based upon the timing discrepancies, cells are substituted into the critical timing path to improve the timing performance of the critical timing path.