Semiconductor package qualification chip

Abstract

A multi-sided, integrated circuit die includes a plurality of read only memory (ROM) circuits, positioned only at the corners of the die, to simplify qualification testing of new package designs. During qualification testing, electrical and environmental stresses are applied to the package and die combination. The package and die are electronically evaluated at predetermined intervals to determine whether a failure has occurred during testing. When a failure occurs during testing, the package and die are diagnosed to isolate and determine the cause or source of the failure. Package design parameters are adjusted accordingly to reduce or eliminate the occurrence of the failures. An optional 12-bit counter is fabricated onto the die for each ROM circuit to exercise the ROM during qualification testing. An optional process monitor is also fabricated onto the die for each ROM circuit to determine the strength of the fabrication process and the resulting quality of circuit elements produced therefrom.