The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 1999

Filed:

Feb. 12, 1997
Applicant:
Inventor:

Shuichi Shirata, Hyogo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06K / ;
U.S. Cl.
CPC ...
39580038 ; 39518207 ; 3951832 ; 39518509 ; 395733 ;
Abstract

A port logical level detection circuit ((81)) detects whether a voltage level of a port (15a) is high or low with respect to a plurality of threshold values. A comparison circuit (82) compares a plurality of detected results with data (S22) held by a port latch (40), and outputs a plurality of comparison results. An accident determination signal generating circuit (83) generates an accident determination signal (S56) from the plurality of comparison results outputted from the comparison circuit (82). Thus, it is possible to determine such an accident that the voltage of the port is at a prescribed logical level of an external circuit (16) or at a level in an indefinite area between prescribed logical levels.


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