Workload balancing in a microprocessor for reduced instruction dispatch

Abstract

A microprocessor employs a set of symmetrical functional units, each of which is coupled into an issue position. Instructions are fetched and aligned to the issue positions. During clock cycles in which fewer than the maximum number of instructions are concurrently selected for dispatch to the issue positions, the microprocessor distributes the selected instructions among the issue positions in order to substantially equalize the number of instructions conveyed to each issue position over a number of clock cycles. For example, the microprocessor may employ a counter, each value of which indicates a different set of issue positions to which instruction(s) are to be distributed. The counter is incremented each time the value is used to select a distribution. The resources in each issue position may be used more efficiently due to the more even distribution of instructions among the issue positions.