System and method for dispatching two instructions to the same execution

Abstract

When the instruction dispatch unit detects two consecutive immediate instructions in the instruction queue directed to the same execution unit, it dispatches both during the same cycle, making use of both GPR ports for the two required GPR operands. Instruction path directing logic directs the first instruction to the execution decoder of the one execution unit during the first occurring cycle and latches the second instruction until a second occurring cycle. It also directs the first immediate operand of the first instruction to a first input of an execution block in the one execution unit during the first occurring cycle. An operand path directing logic directs the first GPR operand referred to by the first instruction to a second input of the execution block during the first occurring cycle and latches a second GPR operand referred to by the second instruction until the second occurring cycle. The instruction path directing logic directs the second instruction to the execution decoder during the second occurring cycle and directs the second immediate operand of the second instruction to the first input of the execution block during the second occurring cycle. The operand path directing logic directs the second GPR operand to the second input of the execution block during the second occurring cycle. In this manner, two instructions are dispatched in a single cycle from the instruction queue to one execution unit of the multiple execution unit parallel computer.