Universal buffered interface for coupling multiple processors, memory

Abstract

A multiprocessor data processing system includes a group of computational data processor nodes including at least one communication data processor node, at least one shared global memory with memory banks, and a number of bus interfaces each coupled between one of a set of local buses and a global bus. Each interface includes a number of input queues and output queues coupled between the local bus and the global bus. The interface supports the use of an inter-processor communication (IPC) mechanism that allows any processor to send an interrupt to any other processor in the system during a single global bus cycle. An interrupt mask is transferred over the address bus during a specially marked bus cycle, with the interrupt mask identifying the processor or processors to be interrupted for interprocessor communication.