The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 1999

Filed:

Aug. 08, 1996
Applicant:
Inventors:

Frank D Ferraiolo, Essex Junction, VT (US);

John E Gersbach, Burlington, VT (US);

Charles J Masenas, Jr, Essex Junction, VT (US);

Norman J Rohrer, Underhill, VT (US);

Bruce W Singer, Richmond, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06K / ; G11B / ;
U.S. Cl.
CPC ...
371-1 ; 371 61 ; 371 62 ;
Abstract

A self-timed circuit for use a clocked logic system is disclosed that comprises a timing detection device for detecting a timing margin of a critical path, the critical path being a path that limits the speed of the system. The circuit further comprises increase logic for increasing the speed of the system clock if the timing margin allows it, and decrease logic for decreasing the speed of the system clock if the timing margin indicates such a need. The increase and decrease logic comprise threshold generator and reset logic, and clock control logic.


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