Memory column redundancy circuit

Abstract

A memory circuit which steers read/write data to a memory array including a plurality of columns (at least one of which is redundant). Coupled to the bit line of each column are a normal mode write transistor and a redundant mode write transistor. If a failing column is detected during manufacturing testing of the memory array, a repair signal for each of the failing column and subsequent columns in the array are de-asserted. When a write operation is performed on the array, an input data bit is provided corresponding to each non-redundant column in the array. The input data bit written to a particular bit line, however, depends upon the state of the repair signal for that column. If the repair signal for a particular column is asserted, the input to the normal mode write transistor is conveyed as write data. Conversely, the input to the redundant mode write transistor is conveyed as write data if the repair signal is de-asserted for a particular column. Similar circuitry is also included to perform steering during a read operation. By proper assertion of the repair signal for each column, the memory circuit causes failing columns to be bypassed during operation of the memory array. The configuration of this memory circuit may advantageously increase the speed of the array for read/write operations. In addition, the loading on each bit line may be decreased, which advantageously decreases write recovery time for the array.