Successive approximation type analog to digital converter with

Abstract

An analog-to-digital converter (ADC) operates repetitively to perform a series of conversion cycles. A comparator (9) receives an analog input signal (V.sub.IN) and compares it with an analog comparison signal produced by a digital-to-analog converter (5). A successive-approximation register circuit (22) holds a digital trial signal value and uses it to control the value of the analog comparison signal in each conversion cycle so as to perform up to two comparisons per cycle, thereby to produce digital data that has a first value ('+1') when the input signal value is greater than a first comparison value (V.sub.C1) and that has a second value ('-1') when the input signal value is less than a second comparison value (V.sub.C2) and that in all other cases has a third value ('0'). The first comparison value (V.sub.C1) is set higher than the trial signal value determined for use in the cycle concerned, and the second comparison value is set lower than that trial signal value. Each comparison value differs from the trial signal value by the same predetermined amount. The successive-approximation register circuit (22) adjusts the trial signal value in each cycle in dependence upon the digital data produced in the cycle concerned so as to tend to bring that value into closer correspondence with the input signal value. Such an ADC can employ the same analog circuits (5,7,9) as a conventional successive-approximation ADC but can operate at higher speeds because errors in the decisions made in one conversion cycle are, within reasonable limits, corrected automatically in subsequent conversion cycles.