Circuit for converting sampling phase of digital data

Abstract

A sampling phase of digital data is converted with having a phase stabilization and a phase alignment. In a converting circuit for converting first digital data synchronized with a fist clock into second digital data synchronized with a second clock not synchronized with the first clock, there are provided; a dividing circuit for dividing 1 (one) time period of the first clock into N time periods ('N' being larger than, or equal to 2); a coefficient setting circuit for setting first and second interpolation coefficients with respect to each of the divided time periods; a data producing circuit for producing the second digital data from data within a certain clock period and data within another clock period subsequent to the certain clock period among the first digital data by using the first and second interpolation coefficients in the divided period where the second clock is located, among the first and second interpolation coefficients set for each of the divided periods.