The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 1999
Filed:
Mar. 03, 1995
Atsuki Taniguchi, Kawasaki, JP;
Fujitsu Limited, Kanagwa, JP;
Abstract
In a first phase-locked loop, a digital value corresponding to the mean frequency of an input clock signal is obtained. In a second phase-locked loop, the mean value of the phase difference of an output clock relative to the input clock is measured and is added to the digital value corresponding to the mean frequency, to obtain a control value. From this control value, a control signal for uniformly controlling a dual-modulus frequency divider is generated and supplied to the dual-modulus frequency divider. In a moving-average circuit, a selector selects input data when updating the contents of a serial latch circuit array, and selects an output of the serial latch circuit array when accumulating values. Values serially output from the latch circuit array for accumulation are successively added up using an adder and a latch circuit. In a division-ratio equalization circuit, a calculating circuit calculates quotients a.sub.0, a.sub.1, a.sub.2 . . . a.sub.m when the control value is expressed as 1/(a.sub.0 +1/(a.sub.1 +1/(a.sub.2 + . . . +1/a.sub.m)) . . . ), and the quotients are set as division ratios in programmable frequency dividers connected in cascade, through which a reference clock signal is frequency-divided to obtain the control signal.