Integrated circuit memory devices having dummy memory cells therein for

Abstract

Integrated circuit memory devices contain an array of active memory cells and at least one column of dummy memory cells having missing electrical connections to either a dummy bit line and/or respective storage electrodes. The dummy memory cells are provided with missing electrical connections so that formation of stray electrical 'shorts' between storage electrodes of dummy and active memory cells during fabrication do not cause memory failures when the memory devices are installed. In particular, integrated circuit memory devices are provided which comprise an array of active DRAM memory cells and a column of dummy DRAM memory cells. The active DRAM memory cells each contain electrical connections to a respective active bit line and a respective storage electrode, but the dummy DRAM memory cells are each devoid of an electrical connection to a dummy bit line and/or a respective storage electrode. Accordingly, the formation of a stringer (e.g., electrical short) between a storage capacitor of an active memory cell and a dummy memory cell does not result in a memory failure even if the word line coupled to the dummy memory cell is activated and the dummy bit line is biased at a potential which is different from the potential of the storage capacitor of the active memory cell.